Method of Making a Graphene Base Transistor With Reduced Collector Area

Method of Making a Graphene Base Transistor With Reduced Collector Area
May 5, 2017 | Source: U.S. Patent and Trademark Office, pdfpiw.uspto.gov, 7 March 2017, Kub, et al.

This disclosure describes a semiconductor transistor device having a graphene base transistor with reduced collector area, and method for fabrication. The graphene base transistor with reduced collector area comprises an electron injection region (the first region), an electron collection region (the third region), and a base region (second region) with the base region consisting of one or more sheets of graphene known as the base graphene material layer region that is intermediate the first and third regions and forms electrical interfaces therewith. The first region comprises an emitter region, and the second region comprises a base region, with typically the emitter region electrically contacting the base region and forming the emitter/base interface. The base region is typically also in electrical contact with the third region material and forms the base/collector interface.

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