Common Problems and Considerations for High-Speed Field-Programmable Gate Array (FPGA) Designs

A field-programmable gate array (FPGA) in a 'development kit' for programming and testing. The FPGA is the large central chip with white paste on it. Source: Author's fieldwork photograph.
Presentation Date: 
June 26, 2019 12:00 pm to 12:45 pm EDT
The Defense Systems Information Analysis Center (DSIAC)

Join us for a live webinar presentation on "Common Problems and Considerations for High-Speed Field-Programmable Gate Array (FPGA) Designs."

FPGA's use in complex sensor systems is growing rapidly.  Radar, communication, navigation, and weapon systems are increasingly relying on the speed, flexibility, and determinism that FPGAs bring to the table for signal and digital signal processing.  Although their usage in complex designs is growing rapidly, a certain mystery still surrounds good practices and techniques for high-speed FPGA designs.  However, the importance of these practices is becoming more important as clock speeds and bandwidths increase.  This webinar will introduce good practices to avoid common problems in FPGA firmware designs.  These techniques are useful for medium and low-speed designs as well.

Participate in the webinar via Skype and/or by phone.

To join the webinar by phone:

  • Please dial: +1 (443)-409-5270
  • Enter conference ID: 94310962

ATTENTION: If you are unable to join the webinar via Skype, you can listen to the presentation by phone. The presentation will be published on the web page 15 minutes prior to the scheduled webinar so that you can download it and follow along with the presentation.

Webinar Instructions:

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